# FICHERO DE ARQUITECTURA DEL REPERTORIO DE INSTRUCCIONES IA16
#
# NEMÓNICOS
#
# RevisiÓn de 30/09/05
# Cada línea no puede tener más de 128 caracteres
#
# Información:
# nemónico
# -t (tipo)
# -1 (modo operando 1 (destino) explícito)
# -2 (modo operando 2 (fuente) explícito)
# -e (implícitos escritos)
# -l (implícitos leídos)
#
# tipo:
# 0 -> transferencia
# 1 -> aritmética
# 2 -> lógica
# 3 -> salto incondicional
# 4 -> salto condicional
# 5 -> prefijo
# 6 -> prefijo segmento
# 7 -> cadenas
# 8 -> control
# 100 -> sin tipo
#
# modos: 0 -> leído 1 -> escrito 2 -> leído y escrito 3 -> no existe
#
# listado impl. escritos: implícito_escrito[:implícito_escrito]
# listado impl. leídos: implícito_leído[:implícito_leído]
#
# [categoría]
# instrucciones
#
# Obligatoriamente la 1ª línea con información debe ser el número de registros
# Número de registros:
99
#
#
# [TRANSFERENCIA]
IN -t 0 -1 1 -2 0 -e -l
LAHF -t 0 -1 3 -2 3 -l SF:ZF:AF:PF:CF -e AH
LDS -t 0 -1 1 -2 0 -e DS -l
LEA -t 0 -1 1 -2 0 -e -l
LES -t 0 -1 1 -2 0 -e ES -l
MOV -t 0 -1 1 -2 0 -e -l
OUT -t 0 -1 0 -2 0 -e -l
POP -t 0 -1 1 -2 3 -e SP -l SP
POPF -t 0 -1 3 -2 3 -e SP:OF:DF:IF:TF:SF:ZF:AF:PF:CF -l SP
PUSH -t 0 -1 0 -2 3 -e SP -l SP
PUSHF -t 0 -1 3 -2 3 -l SP:OF:DF:IF:TF:SF:ZF:AF:PF:CF -e SP
SAHF -t 0 -1 3 -2 3 -e SF:ZF:AF:PF:CF -l AH
XCHG -t 0 -1 2 -2 2 -e -l
XLAT -t 0 -1 3 -2 3 -l BX:AL -e AL
# [PROCESO]
# [ARITMETICAS]
AAA -t 1 -1 3 -2 3 -l AF:AX -e AF:CF:AX
AAD -t 1 -1 3 -2 3 -l AX -e SF:ZF:PF:AX
AAM -t 1 -1 3 -2 3 -l AL -e SF:ZF:PF:AX
AAS -t 1 -1 3 -2 3 -e AF:CF:AX -l AX:AF
ADC -t 1 -1 2 -2 0 -l CF -e OF:SF:ZF:AF:PF:CF
ADD -t 1 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
CBW -t 1 -1 2 -2 3 -l AL -e AX
CMP -t 1 -1 0 -2 0 -e OF:SF:ZF:AF:PF:CF -l
CWD -t 1 -1 2 -2 3 -l AX -e AX:DX
DAA -t 1 -1 3 -2 3 -l AL:AF:CF -e OF:SF:ZF:AF:PF:CF:AL
DAS -t 1 -1 3 -2 3 -l AL:AF:CF -e SF:ZF:AF:PF:CF:AL
DEC -t 1 -1 2 -2 3 -e OF:SF:ZF:AF:PF -l
DIV -t 1 -1 2 -2 3 -l DX:AX -e OF:SF:ZF:AF:PF:CF:AX:DX
IDIV -t 1 -1 2 -2 3 -l DX:AX -e OF:SF:ZF:AF:PF:CF:AX:DX
IMUL -t 1 -1 2 -2 3 -l AX -e OF:SF:ZF:AF:PF:CF:DX:AX
INC -t 1 -1 2 -2 3 -e OF:SF:ZF:AF:PF -l
MUL -t 1 -1 2 -2 3 -l AX -e OF:SF:ZF:AF:PF:CF:DX:AX
NEG -t 1 -1 2 -2 3 -e OF:SF:ZF:AF:PF:CF -l
SBB -t 1 -1 2 -2 0 -l CF -e OF:SF:ZF:AF:PF:CF
SUB -t 1 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
# [LOGICAS]
AND -t 2 -1 2 -2 0 -e OF:SF:ZF:PF:CF -l
NOT -t 2 -1 2 -2 3 -e -l
OR -t 2 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
RCL -t 2 -1 2 -2 0 -e OF:CF -l
RCR -t 2 -1 2 -2 0 -e OF:CF -l
ROL -t 2 -1 2 -2 0 -e OF:CF -l
ROR -t 2 -1 2 -2 0 -e OF:CF -l
SHL/SAL -t 2 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
SAR -t 2 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
SHR -t 2 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
TEST -t 2 -1 0 -2 0 -e OF:SF:ZF:AF:PF:CF -l
XOR -t 2 -1 2 -2 0 -e OF:SF:ZF:AF:PF:CF -l
# [BIFURCACIONES]
CALL -t 3 -1 0 -2 3 -l CS:IP:SS:SP -e PILA:CS:IP:SP
JMP -t 3 -1 0 -2 3 -e CS:IP -l
JB/JNAE -t 4 -1 0 -2 3 -l CF -e IP
JBE/JNA -t 4 -1 0 -2 3 -l CF:ZF -e IP
JCXZ -t 4 -1 0 -2 3 -l CX -e IP
JE/JZ -t 4 -1 0 -2 3 -l ZF -e IP
JL/JNGE -t 4 -1 0 -2 3 -l SF:OF -e IP
JLE/JNG -t 4 -1 0 -2 3 -l ZF:SF:OF -e IP
JNB/JAE -t 4 -1 0 -2 3 -l CF -e IP
JNBE/JA -t 4 -1 0 -2 3 -l CF:ZF -e IP
JNE/JNZ -t 4 -1 0 -2 3 -l ZF -e IP
JNL/JGE -t 4 -1 0 -2 3 -l SF:OF -e IP
JNLE/JG -t 4 -1 0 -2 3 -l ZF:SF:OF -e IP
JNO -t 4 -1 0 -2 3 -l OF -e IP
JNP/JPO -t 4 -1 0 -2 3 -l PF -e IP
JNS -t 4 -1 0 -2 3 -l SF -e IP
JO -t 4 -1 0 -2 3 -l OF -e IP
JP/JPE -t 4 -1 0 -2 3 -l PF -e IP
JS -t 4 -1 0 -2 3 -l SF -e IP
LOOP -t 4 -1 0 -2 3 -l CX -e CX:IP
LOOPNZ/LOOPNE -t 4 -1 0 -2 3 -l CX:ZF -e CX:IP
LOOPZ/LOOPE -t 4 -1 0 -2 3 -l CX:ZF -e CX:IP
RET -t 3 -1 0 -2 3 -l PILA:SS:SP -e CS:IP:SP
RETF -t 3 -1 0 -2 3 -l PILA:SS:SP -e CS:IP:SP
# [CADENAS]
CMPS -t 7 -1 3 -2 3 -l DS:SI:ES:DI:DF -e OF:SF:ZF:AF:PF:CF:SI:DI
LODS -t 7 -1 3 -2 3 -l DS:SI:DF -e AX:SI
MOVS -t 7 -1 3 -2 3 -l DS:SI:ES:DI:DF -e SI:DI
REP -t 5 -1 3 -2 3 -l CX -e CX:IP
REPZ/REPE -t 5 -1 3 -2 3 -l CX:ZF -e CX:IP
REPNZ/REPNE -t 5 -1 3 -2 3 -l CX:ZF -e CX:IP
SCAS -t 7 -1 3 -2 3 -l AX:ES:DI:DF -e OF:SF:ZF:AF:PF:CF:DI
STOS -t 7 -1 3 -2 3 -l AX:ES:DI:DF -e DI
# [OTRAS]
INT -t 3 -1 0 -2 3 -l AX:CS:IP:SS:SP:OF:DF:IF:TF:SF:ZF:AF:PF:CF -e AX:DX:PILA
INT 3 -t 3 -1 0 -2 3 -l CS:IP:SS:SP:OF:DF:IF:TF:SF:ZF:AF:PF:CF -e PILA
INTO -t 4 -1 0 -2 3 -l OF -e
IRET -t 3 -1 3 -2 3 -l PILA:SS:SP -e CS:IP:SP:OF:DF:IF:TF:SF:ZF:AF:PF:CF
CLC -t 8 -1 3 -2 3 -e CF -l
CLD -t 8 -1 3 -2 3 -e DF -l
CLI -t 8 -1 3 -2 3 -e IF -l
CMC -t 8 -1 3 -2 3 -e CF -l CF
ESC -t 8 -1 0 -2 3 -e -l
HLT -t 8 -1 3 -2 3 -e -l
LOCK -t 5 -1 3 -2 3 -e -l
NOP -t 8 -1 3 -2 3 -e -l
STC -t 8 -1 3 -2 3 -e CF -l
STD -t 8 -1 3 -2 3 -e DF -l
STI -t 8 -1 3 -2 3 -e IF -l
WAIT -t 8 -1 3 -2 3 -e -l
CS -t 6 -1 3 -2 3 -e -l
DS -t 6 -1 3 -2 3 -e -l
ES -t 6 -1 3 -2 3 -e -l
SS -t 6 -1 3 -2 3 -e -l
(086)? -t 100 -1 3 -2 3 -e -l
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